In general, the present invention relates to a television-signal processing apparatus and a television signal processing method. In particular, the present invention relates to a television-signal processing apparatus and a television signal processing method wherein time-axis correction is carried out for removing jitters from a television signal by generating a television signal that maximizes correlation between a carrier chrominance signal for a predetermined scanning line constituting a predetermined field and a carrier chrominance signal for a scanning line adjacent thereto.
A television (TV) signal broadcasted by a television broadcasting station or a TV signal played back by an analog VCR (Video Cassette Recorder) includes time-axis variations known as jitters. If a TV signal including jitters is displayed on a monitor as it is, lines are vibrating to the right and left, making it impossible to obtain good-quality pictures.
FIG. 12 is a diagram showing three continuous lines of carrier chrominance signal in a predetermined field of a TV signal including jitters. In the figure, 198th, 200th and 202nd lines of carrier chrominance signal in a predetermined (even) field are shown as a solid line, a fine dotted line and a rough dotted line respectively.
Since the phase of the carrier chrominance signal of each line is modulated by a chrominance signal for the line, the phase basically varies from line to line. Since there is correlation between adjacent lines, however, the correlation value is relatively large even though the correlation value decreases due to the existence of jitters.
The correlation value between the carrier chrominance signals of the 198th and 202nd lines, the correlation value between the carrier chrominance signals of the 198th and 200th lines, and the correlation value between the carrier chrominance signals of the 200th and 202nd lines shown in FIG. 12 are found to be 0.913390, -0.103358 and -0.104299 respectively.
As described above, the correlation value between the carrier chrominance signals of the 198th and 202nd lines is positive but the correlation value between the carrier chrominance signals of the 198th and 200th lines and the correlation value between the carrier chrominance signals of the 200th and 202nd lines are negative. This is because, in the case of the former correlation value, the carrier chrominance signals have the same reference phase while, for each of the latter two correlation values, the carrier chrominance signals have reference phases opposite to each other.
The larger the absolute value of a correlation value, the smaller the effect of jitters and, thus, the more the phases of the carrier chrominance signals represented by the correlation value match each other. For example, the absolute values of the correlation value between the carrier chrominance signals of the 198th and 200th lines and that between the carrier chrominance signals of the 200th and 202nd lines are 0.103358 and 0.104299 respectively which are not large enough in comparison with the absolute value 0.913390 of the correlation value between the carrier chrominance signals of the 198th and 202nd lines.
In order to solve the problem, equipment for business applications and high-end equipment for general consumers employ a TBC (Time Base Corrector) for removing jitters from a TV signal.
FIG. 13 is a block diagram showing a typical configuration of the related art TBC 1.
As shown in the figure, a TV signal broadcasted by a TV broadcasting station or a TV signal played back by a VCR such as a home VCR is supplied to an H/V synchronization separating circuit 11 and an A/D conversion circuit 12 employed in the TBC 1. The H/V synchronization separating circuit 11 is used for extracting horizontal-synchronization (H) and vertical-synchronization (V) signals from the TV signal and outputting the extracted horizontal-synchronization (H) and vertical-synchronization (V) signals to a write-clock generating circuit 13.
The write-clock generating circuit (PLL) 13, a kind of PLL circuit, uses the extracted horizontal-synchronization (H) and vertical-synchronization (V) signals for generating a write clock signal and supplying the write clock signal to the A/D conversion circuit 12 and a write-address counter 15. Driven by the write clock signal supplied from the write-clock generating circuit 13, the A/D conversion circuit 12 converts the analog TV signal into a digital one and supplies the digital signal to a memory unit 14.
In synchronization with the write clock signal supplied from the write-clock generating circuit 13, the write-address counter 15 increments a counter value thereof, supplying the incremented counter value to the memory unit 14 as an address. The memory unit 14 stores the digital signal supplied thereto by the A/D conversion circuit 12 at an address indicated by the incremented counter value supplied thereto by the write-address counter 15.
A read-clock generating circuit 19 comprises, among other components, a fixed-frequency crystal oscillating circuit for outputting a read clock signal having a constant frequency to a D/A conversion circuit 16 and a read-address counter 17.
A jump detecting circuit 18 detects a difference between a write address, a counter value output by the write-address counter 15, and a read address, a counter value output by the read-address counter 17. When the difference which ideally has a fixed value goes beyond a predetermined range, the jump detecting circuit 18 controls the read-address counter 17 in such a way that the difference returns to a value in the predetermined range.
In synchronization with the read clock signal supplied from the read-clock generating circuit 19, the read-address counter 17 increments a counter value thereof, supplying the incremented counter value to the memory unit 14 as an address. The memory unit 14 reads digital data at an address indicated by the incremented counter value supplied thereto by the read-address counter 17, supplying the digital data to the D/A conversion circuit 16. The D/A conversion circuit 16 converts the digital data supplied thereto by the memory unit 14 into an analog signal, outputting the analog signal to a signal processing circuit.
In this way, the horizontal-synchronization (H) and vertical-synchronization (V) signals extracted from a TV signal are used for generating a write clock signal locked to the phase of the carrier chrominance signal. The write clock signal is in turn used for writing digital data into the memory unit 14 which is then read out back by using a read clock signal with a fixed phase in order to remove jitters from the TV signal.
There is raised a problem, however, that a method using a TBC with a configuration described above is the only related art technique for reducing the number of jitters included in a TV signal, leaving no other alternative. In addition, when a TBC designed for equipment for business applications is applied to equipment for general consumers as has been done traditionally so far, a special circuit such as a chroma conversion circuit is required, giving rise to a problem of entailing a circuit configuration with an increased size.